I. Field of the Disclosure
The technology of the disclosure relates generally to an instruction cache for a processor.
II. Background
Commonly owned and assigned U.S. Pat. No. 7,337,272 teaches, among other things, an instruction cache 10 for a processor, where the instruction cache 10 includes extended cache lines 12-0 through 12-NUMECL, as illustrated in FIG. 1. The extended cache lines 12-0 through 12-NUMECL are generally referred to herein collectively as the extended cache lines 12 and individually as the extended cache line 12. As illustrated, each of the extended cache lines 12 includes a main cache line portion 14 and an extra data portion 16. The main cache line portion 14 stores a predefined number of words (e.g., 16 words or 64 bytes) and operates to cache instruction data from a line of memory. The extra data portion 16 of each extended cache line 12 is located at the end of the extended cache line 12 and is a copy of instruction data at a start of a next line of memory, which may also be a copy of a start of the next extended cache line 12. So, for example, assume that the main cache line portion 14 of the extended cache line 12-0 caches instruction data from a first line of memory and the main cache line portion 14 of the extended cache line 12-1 caches instruction data from a second line of memory that immediately follows the first line of memory. In this example, the extra data portion 16 of the extended cache line 12-0 stores a copy of the instruction data at the start of the main cache line portion 14 of the extended cache line 12-1. Notably, the main cache line portions 14 and the extra data portions 16 of the extended cache lines 12 may be implemented within the same physical resource (i.e., part of the same physical cache memory) or implemented within separate physical resources.
The instruction cache 10 having the extended cache lines 12 is particularly beneficial in processors that allow variable length instructions (e.g., processors that allow both 16-bit and 32-bit instructions). Variable length instructions result in instructions that are not word-aligned (i.e., non-word-aligned instructions). Further, variable length instructions result in instructions that cross line boundaries in the instruction cache, which are referred to herein as line-crossing instructions. For conventional instruction caches, fetching a line-crossing instruction from the instruction cache requires two separate fetch operations, namely, a first fetch to obtain a first portion of the instruction from a first cache line, and second fetch to obtain a second portion of the instruction from a second cache line. In contrast, the instruction cache 10 having the extended cache lines 12 enables fetching of a line-crossing instruction using a single fetch operation from a single extended cache line 12.
As an example, consider an implementation where instructions can be either 16-bit instructions or 32-bit instructions, and lines of memory and thus the main cache line portion 14 of the extended cache lines are 16 words (i.e., 64 bytes). Due to the variable length instructions, there will be situations where the first 16-bits of a 32-bit instruction reside in one line of memory and the second 16-bits of the 32-bit instruction reside in the next line of memory. When caching the instruction in the instruction cache 10, the first 16-bits of the instruction are cached as the last 16-bits of the main cache line portion 14 of one of the extended cache lines 12, and a copy of the last 16-bits of the 32-bit instruction is cached in the extra data portion 16 of the same extended cache line 12. By storing a copy of the last 16-bits of the 32-bit instruction as extra data in the extra data portion 16 of the extended cache line 12, the full 32-bit instruction can be fetched using a single fetch of the extended cache line 12.
One issue with the instruction cache 10 is that a page-crossing instruction may span two pages of memory having different translation information (e.g., different execution permissions). More specifically, the instruction cache 10 is utilized to cache instruction data that resides in memory that is organized into a number of memory pages. A line-crossing instruction that crosses from a last line in one page of memory to a first line in another page of memory is referred to herein as a page-crossing instruction. When a page-crossing instruction is cached in the instruction cache 10, the first part of the page-crossing instruction is cached at the end of the main cache line portion 14 of one of the extended cache lines 12, and a copy of the last part of the page-crossing instruction is cached as extra data in the extra data portion 16 of the same extended cache line 12. As a result, the page-crossing instruction can be fetched from the instruction cache 10 using a single fetch from one extended cache line 12. As an example, FIG. 1 illustrates a page-crossing instruction having a first part (PCI(1)) that resides at the end of a last line of memory in one page of memory and is cached at the end of the main cache line portion 14 of the extended cache line 12-X, and a second part (PCI(2)) that resides at the start of a first line of memory in another page of memory and is cached at the start of the main cache line portion 14 of the extended cache line 12-(X+1). A copy of the second part (PCI(2)) of the page-crossing instruction is stored as extra data in the extra data portion 16 of the extended cache line 12-X. As such, the page-crossing instruction can then be fetched by fetching the extended cache line 12-X.
One issue that arises when dealing with page-crossing instructions is that a page-crossing instruction fetched from a single extended cache line 12 may have a first part that resides in one page of memory having certain page attributes (e.g., certain execution permissions) and a second part that resides in a different page of memory having different page attributes (e.g., different execution permissions). For example, the first part (PCI(1)) of the page-crossing instruction cached in the extended cache line 12-X may reside in a page of memory that has different execution permissions than the page of memory in which the second part (PCI(2)) resides. Therefore, systems and methods are needed to process page-crossing instructions obtained from an instruction cache having extended cache lines.